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Operation Description
The FL6300A PWM controller integrates features to
enhance the performance of flyback converters. An
internal valley voltage detector ensures Quasi-Resonant
(QR) operation across a wide range of line voltage.
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
R HV , which are recommended as 1N4007 and 100 k ? .
Typical startup current drawn from the HV pin is 1.2 mA
and it charges the hold-up capacitor through the diode
and resistor. When the V DD voltage level reaches V DD-ON ,
the startup current switches off. At this point, the V DD
capacitor only supplies the FL6300A to maintain V DD until
the auxiliary winding of the main transformer provides
the operating current.
Valley Detection
The DET pin is connected to an auxiliary winding of the
transformer via resistors of the divider to generate a
valley signal once the secondary-side switching current
discharges to zero. It detects the valley voltage of the
switching waveform to achieve the valley voltage
switching. This ensures QR operation, minimizes
switching losses, and reduces EMI. Figure 17 shows
divider resistors R DET and R A . R DET is recommended as
150 k ? to 220 k ? to achieve valley voltage switching.
When V AUX (in Figure 17) is negative, the DET pin
voltage is clamped to 0.3 V.
Green-Mode Operation
The proprietary green mode provides off-time modulation
to linearly decrease the switching frequency under light-
load conditions. V FB , which is derived from the voltage
feedback loop, is taken as the reference. In Figure 19,
once V FB is lower than V N , t OFF-MIN increases linearly with
lower V FB . The valley voltage detection signal does not
start until t OFF-MIN finishes. Therefore, the valley-detect
circuit is active until t OFF-MIN finishes, which decreases the
switching frequency and provides extended valley
voltage switching. However, in very light-load condition, it
might fail to detect the valley voltage after the t OFF-MIN
expires. Under this condition, an internal t TIME-OUT signal
initiates a new cycle after a 9 μ s delay. Figure 20 and
Figure 21 show the two conditions.
t O F F -M I N
2 .1 m s
38/13 μ s
8 /3 μ s
1 .2 V
2 .1 V
V FB
Figure 19. V FB vs. t OFF-MIN Curve
Figure 17. Valley Detect Section
The internal timer (minimum t OFF ) prevents gate
retriggering within 8 μs after the gate signal going-LOW
transition. The minimum t OFF limit prevents system
frequency being too high. Figure 18 shows a typical drain
voltage waveform with first valley switching.
Figure 18. First Valley Switching
? 2010 Fairchild Semiconductor Corporation
FL6300A ? Rev. 1.0.2
10
Figure 20. QR Operation in Extended Valley Voltage
Detection Mode
Figure 21. Internal t TIME-OUT Initiates New Cycle After
Failure to Detect Valley Voltage
www.fairchildsemi.com
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